In the manufacturing of semiconductor devices, there is a continuing drive to increase device density on the semiconductor chips in order to increase the resulting operating speeds of the device. As semiconductor technologies scale to support higher chip density, Middle of Line (MOL) connections such as stud contacts become narrower, and thus become more resistive. These higher resistances lead to a significant degradation in chip performance. MOL semiconductor processing techniques create structures that electrically connect an intrinsic semiconductor device, such as a metal-oxide-semiconductor-field effect transistor MOSFET), with Back-End-of-Line (BEOL) chip wiring. It is therefore imperative that improved MOL processes and structures be utilized that do not suffer the same shortcomings as those found today.